Many of today's integrated memory circuits include redundant memory cells that are available to replace malfunctioning or defective matrix memory cells. Typically, the entire matrix row or column to which a defective memory cell belongs is identified as defective and is respectively replaced with a redundant row or column. Often, one defective matrix row or column alone can cause a memory circuit to memory circuits, engineers can repair otherwise unusable memory circuits and increase the overall manufacturing yield of operational memory circuits.
Typically, engineers test a memory circuit shortly after it is manufactured to find and identify rows and columns that contain defective memory cells. For example, after a test station identifies a defective column, it maps a redundant column to the address of the defective column. During normal operation of the memory circuit when an external circuit, such as a processor, writes data to the address of a memory cell in the defective column via a data bus, a redundancy circuit within the memory circuit isolates the defective column from the data bus and diverts the data to a corresponding memory cell in the redundant column. The redundancy circuit within the memory circuit performs this isolation and diversion in a manner that is transparent to the external circuit.
Often, select circuits such as programmable multiplexers are used to enable a selected redundant memory row or column to replace a defective matrix row or column, respectively. For example, FIG. 1 is a schematic diagram of a known multiplexer circuit 1, which, when in an unprogrammed state, disables a corresponding redundant row or column, and which, when in a programmed state, enables the redundant row or column in response to the desired one of n select signals S.sub.0 -S.sub.n-1. For example, if the corresponding redundant row or column is to be enabled whenever S.sub.1 is active logic 1, all the selectively conductive elements F.sub.0 -F.sub.n-1, such as fuse elements, are made nonconductive except the element F.sub.1, which is made conductive. When S.sub.1 is active logic 1, the transistor T.sub.1 is active, and thus pulls the node Na to an active logic 0. A pair 2 of serially coupled inverters, which together act as a noninverting buffer, provides the active logic 0 at the output of the multiplexer 1 to enable the redundant row or column. When S.sub.1 is inactive logic 0, the transistor T.sub.1 is inactive and the transistor T.sub.p pulls up the node Na to an inactive logic 1, which the multiplexer 1 provides to disable the redundant row or column.
One problem with many such select circuits is that they occupy a relatively large area of the memory device. Because the memory device typically includes many of these select circuits, the area that they occupy may significantly increase the production costs of the memory device.
Further background on memories, redundant memory cells, and redundancy circuits can be found in: Prince, Betty, Semiconductor Memories, A Handbook of Design, Manufacture, and Applications, 2nd Edition, John Wiley and Sons, (1991); Hardee et al., "A Fault-Tolerant 30 ns/375 mW 16K X 1 NMOS Static RAM," Journal of Solid State Circuits SC-16(5):435-43 (IEEE, 1981); Childs et al., "An 18 ns 4K X 4 CMOS SRAM," Journal of Solid State Circuits SC-19(5):545-51 (IEEE, 1984); and ISSCC Proceedings From 1975 to the present, all of which are incorporated herein by reference.